Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho

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Nanoscale process variations in conventional SRAM cells are known to limit voltage scaling in microprocessor caches. Recently, a number of novel cache architectures have been proposed which substitute faulty words of one cache line with healthy words of others, to tolerate these failures at low voltages. These schemes rely on the fault maps to identify faulty words, inevitably increasing the chip area. Besides, the relationship between word sizes and the cache failure rates is not well studied in these works. In this paper, we analyze the word substitution schemes by employing Fault Tree Model and Collision Graph Model. A novel cache architecture (Macho) is then proposed based on this model. Macho is dynamically reconfigurable and is locally optimized (tailored to local fault density) using two algorithms: 1) a graph coloring algorithm for moderate fault densities and 2) a bipartite matching algorithm to support high fault densities. An adaptive matching algorithm enables on-demand reconfiguration of Macho to concentrate available resources on cache working sets. As a result, voltage scaling down to 400 mV is possible, tolerating bit failure rates reaching 1 percent (one failure in every 100 cells). This near-threshold voltage (NTV) operation achieves 44 percent energy reduction in our simulated system (CPU+DRAM models) with a 1 MB L2 cache.
Publisher
IEEE COMPUTER SOC
Issue Date
2015-06
Language
English
Article Type
Article
Keywords

CMOS; OPERATION; DESIGN; MODEL; SRAM

Citation

IEEE TRANSACTIONS ON COMPUTERS, v.64, no.6, pp.1694 - 1706

ISSN
0018-9340
DOI
10.1109/TC.2014.2339813
URI
http://hdl.handle.net/10203/199084
Appears in Collection
CS-Journal Papers(저널논문)
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