A W-Band High-Efficiency CMOS Differential Current-Reused Frequency Doubler

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A W-band differential frequency doubler using a current-reuse configuration in a 65 nm CMOS process is presented in this letter. The differential current-reuse circuit with a second harmonic coupling transformer is introduced to improve conversion gain at small input powers minimizing the effect of the RF bypass capacitor. The proposed circuit achieves a conversion gain of 0.8 similar to -4.2 dB and a fundamental rejection above 19 dB in the input frequency range of 36.5 similar to 44 GHz with -4 dBm input power. It has conversion gain variation below 1 dB when the input power varies from -7.4 to 0.1 dBm at 77 GHz. The dc power consumption is 14 mW. It has the highest conversion gain with the smallest chip size of 0.22 mm(2) among all V-/W-band CMOS frequency doublers.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2015-05
Language
English
Article Type
Article
Keywords

MU-M CMOS; POWER; DBM

Citation

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.25, no.5, pp.307 - 309

ISSN
1531-1309
DOI
10.1109/LMWC.2015.2409773
URI
http://hdl.handle.net/10203/198777
Appears in Collection
EE-Journal Papers(저널논문)
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