Topology-oriented pattern extraction and classification for synthesizing lithography test patterns

A small but diverse set of test patterns is essential for the optimization of lithography parameters. We selectively extract the complicated patterns that are likely to cause lithography defects from test layouts. These patterns are hierarchically classified into groups based on geometric similarity; then, a small number of patterns are chosen to represent each group. We demonstrate this approach in the synthesis of test patterns for metal layers. The total area of the resulting test patterns is only 10% of that of a set produced using a more conventional technique; the resulting hotspot library has 30% fewer patterns, and the time required to create it is cut by an order of magnitude.
Publisher
SPIE-SOC PHOTO-OPTICAL INSTRUMENTATION ENGINEERS
Issue Date
2015-01
Language
ENG
Citation

JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, v.14, no.1

ISSN
1932-5150
DOI
10.1117/1.JMM.14.1.013503
URI
http://hdl.handle.net/10203/198257
Appears in Collection
EE-Journal Papers(저널논문)
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