Security considerations in processor interconnect design

Abstract

Recently, large parallel computing systems are designed based on multiple SMP machines with various software stacks such as MPI and SHMEM. Each SMP machine consist of multiple processor and all processor in the system are connected with high bandwidth interconnect network. There are two most popular processor interconnect technologies currently, Intel QPI and AMD hypertransport. These the-state-of-the-art technologies have a vulnerability of router design, which can cause new type of performance attacks. In this study, we observe the-state-of-the-art processor interconnect network has architectural vulnerability and introduce a performance attack using by routing table attack. We further show how much this attack can degrade performance and how the network can be protected. Our study propose a new routing protocol suitable for processor interconnect networks to protect this vulernability.