DC to 12.5Gbps continuous-rate and referenceless CDR circuit

Abstract

The continuous-rate CDR circuit has been proposed to support Ethernet and other communication standards. The wide frequency range ring VCO or 2 LC VCO, however, are needed to cover the continuous-rate operation. The high phase noise or the huge area consumption is a trade-off in the previous researches.This proposed circuit achieves DC to 12.5Gbps continuous-rate CDR circuit with the only one LC VCO and the fractional divider. The radix-2 based fractional divider is implemented with the integer divider for the simplicity and the asynchronous clock based calibration loop is also implemented to alleviate the phase mis-match due to the poly phase filter and 8 phase generator. The proposed CDR circuit uses SRCG based FLL and removes the risk of the harmonic lock. In addition, the phase rotator based 4 parallel CDR structure is implemented to support the recent Ethernet and other communication standards with the other needed cir-cuits which are the analog front end, transmitter and so on. The proposed CDR is implemented in 90nm CMOS process. This continuous-rate and referenceless CDR circuit can operate with any input data-rate within 12.5Gbps without the external reference clock and the clean eye diagram can be shown at the transmitter output. The total power consumption of this CDR circuit is 560mW. The FoM of this is 7mW/Gb/s. The area consumption is 3.45mm2.