Fabrication of Si and SiGe junctionless bulk FinFETs using junction-isolation and research on their transistor characteristics접합분리를 이용한 실리콘 및 실리콘저마늄 채널의 무접합 벌크 핀펫 소자에 대한 제작 및 그 트랜지스터 특성에 대한 연구

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This dissertation focuses on the fabrication of Si and SiGe channel junctionless (JL) bulk FinFETs using junction-isolation technique and the research on their transistor characteristics in order to overcome the challenge in the formation of ultra-shallow and abrupt source/drain (S/D) junction which is inevitably required in the conventional inversion-mode (IM) FET as a result of the recent drastic scaling-down of the CMOS device geometries. For that purpose, we experimentally demonstrated JL and junctionless accumulation mode (JAM) bulk FinFETs successfully for the first time using the virtue of body-tied FET and characterized their transistor properties in detail from the viewpoint of gate electrostatics, mobility scalability, junction-isolation, back bias/temperature dependency, and parasitic bipolar junction transistor (BJT)-induced behavior. Finally, we conducted the in-depth simulation studies on JL and JAM bulk FinFET including the comparison with JL SOI FinFET. In respect of the gate electrostatics, we achieved the Si and SiGe channel JAM bulk FinFETs with the channel dimensions such as fin width ($W_{fin}$) = 20 nm, fin height ($H_{fin}$) = 20/50 nm and gate length ($L_G$) = 180 nm, showing the excellent subthreshold characteristics such as swing (SS) ≤ 70 mV/dec and drain-induced barrier lowering (DIBL) ≤ 40 mV/V by introducing the gate stack comprising $HfO_2$ gate dielectric and TiN gate electrode. As either $W_{fin}$ decreases or $L_G$ increases, the gate electrostatics represented by SS and DIBL improves and the threshold voltage ($V_{th}$) increases. In addition, the SiGe channel JAM FET shows a superior DIBL to that of Si channel JAM FET because SiGe has a higher dielectric constant than that of Si, leading to the more improved gate electrostatics despite the degradation of literal DIBL (i.e. the channel immunity to the drain-induced electric field) especially in case of multi-gate 3D FET scheme. As $W_{fin}$ decreases, the mobility is enhanced...
Advisors
Lee, Seok-Heeresearcher이석희
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2014
Identifier
591825/325007  / 020105312
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 2014.8, [ viii, 119 p. ]

Keywords

Junctionless (JL) FET; 쇼클리-리드-홀 생성/소멸 전류; 역전압 인가 다이오드 누설전류; 기생 바이폴라 접합 트랜지스터; 제로 온도 계수; 접합 분리된 바디-타이드 소자; junctionless-accumulation-mode (JAM) FET; Si and SiGe channel FinFET; junction isolated body-tied FET; zero temperature coefficient (ZTC); parasitic bipolar junction transistor (BJT); pn diode reverse-biased leakage current; Shockley-Read-Hall (SRH) R-G current; 무접합 소자; 무접합 축적 모드 소자; 실리콘 및 실리콘저마늄 채널 소자

URI
http://hdl.handle.net/10203/196597
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=591825&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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