A novel hardware architecture of intra-predictor generator for H.264/AVC codec

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The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work [3].
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2008-07
Language
English
Article Type
Article; Proceedings Paper
Citation

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E91D, no.7, pp.2083 - 2086

ISSN
0916-8532
DOI
10.1093/ietisy/e91-d.7.2083
URI
http://hdl.handle.net/10203/195934
Appears in Collection
GT-Journal Papers(저널논문)
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