Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation

Aggressive reduction of timing margins, called timing speculation, is an effective way of reducing the supply voltage for a pipeline circuit and thereby its power consumption. However, probability of timing error increases with the voltage scaling and hence, the errors must be corrected with small cycle penalty. We introduce an improved Razor flip-flop which makes more effective use of its shadow latch, so that a pipeline stage can correct an error while continuing to receive data. This avoids the need for repeated clock gating when timing errors happen simultaneously at different stages, or when an error persists. The new flip-flop also facilitates time-borrowing. Our technique uses less energy than the state-of-the art technique, and the energy saving increases with pipeline length: with 10 stages, 4-9% smaller energy is used.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2015-02
Language
ENG
Keywords

DYNAMIC VARIATION TOLERANCE; CIRCUITS

Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.2, pp.468 - 477

ISSN
1549-8328
DOI
10.1109/TCSI.2014.2364691
URI
http://hdl.handle.net/10203/195610
Appears in Collection
EE-Journal Papers(저널논문)
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