DC Field | Value | Language |
---|---|---|
dc.contributor.author | Won, Hyosup | ko |
dc.contributor.author | Yoon, Taehun | ko |
dc.contributor.author | Han, Jinho | ko |
dc.contributor.author | Lee, Joon-Yeong | ko |
dc.contributor.author | Yoon, Jong-Hyeok | ko |
dc.contributor.author | Kim, Taeho | ko |
dc.contributor.author | Lee, Jeong-Sup | ko |
dc.contributor.author | Lee, Sangeun | ko |
dc.contributor.author | Han, Kwangseok | ko |
dc.contributor.author | Lee, Jinhee | ko |
dc.contributor.author | Park, Jinho | ko |
dc.contributor.author | Bae, Hyeon-Min | ko |
dc.date.accessioned | 2015-04-08T04:21:45Z | - |
dc.date.available | 2015-04-08T04:21:45Z | - |
dc.date.created | 2014-11-24 | - |
dc.date.created | 2014-11-24 | - |
dc.date.created | 2014-11-24 | - |
dc.date.issued | 2015-02 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.2, pp.399 - 413 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/195523 | - |
dc.description.abstract | This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay-and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mV(ppd) to 1.06 V-ppd. RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10(-12) is 42 mV(ppd). The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10(-15) on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | 1/16 DEMULTIPLEXER | - |
dc.subject | TECHNOLOGY | - |
dc.subject | CLOCK | - |
dc.subject | INTERFACE | - |
dc.subject | GAIN | - |
dc.title | A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS | - |
dc.type | Article | - |
dc.identifier.wosid | 000349231400001 | - |
dc.identifier.scopusid | 2-s2.0-85027942026 | - |
dc.type.rims | ART | - |
dc.citation.volume | 50 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 399 | - |
dc.citation.endingpage | 413 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2014.2369494 | - |
dc.contributor.localauthor | Bae, Hyeon-Min | - |
dc.contributor.nonIdAuthor | Kim, Taeho | - |
dc.contributor.nonIdAuthor | Lee, Jeong-Sup | - |
dc.contributor.nonIdAuthor | Lee, Sangeun | - |
dc.contributor.nonIdAuthor | Han, Kwangseok | - |
dc.contributor.nonIdAuthor | Lee, Jinhee | - |
dc.contributor.nonIdAuthor | Park, Jinho | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Clock and data recovery (CDR) | - |
dc.subject.keywordAuthor | delay-and phase-locked loop (D/ PLL) | - |
dc.subject.keywordAuthor | input sensitivity | - |
dc.subject.keywordAuthor | jitter tolerance (JTOL) | - |
dc.subject.keywordAuthor | jitter transfer (JTRAN) | - |
dc.subject.keywordAuthor | low power | - |
dc.subject.keywordAuthor | phase rotator | - |
dc.subject.keywordAuthor | serial link | - |
dc.subject.keywordAuthor | transceiver | - |
dc.subject.keywordAuthor | 100 Gigabit Ethernet | - |
dc.subject.keywordPlus | 1/16 DEMULTIPLEXER | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
dc.subject.keywordPlus | CLOCK | - |
dc.subject.keywordPlus | INTERFACE | - |
dc.subject.keywordPlus | CIRCUIT | - |
dc.subject.keywordPlus | GAIN | - |
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