A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

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This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay-and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mV(ppd) to 1.06 V-ppd. RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10(-12) is 42 mV(ppd). The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10(-15) on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2015-02
Language
English
Article Type
Article
Keywords

1/16 DEMULTIPLEXER; TECHNOLOGY; CLOCK; INTERFACE; GAIN

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.2, pp.399 - 413

ISSN
0018-9200
DOI
10.1109/JSSC.2014.2369494
URI
http://hdl.handle.net/10203/195523
Appears in Collection
EE-Journal Papers(저널논문)
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