Miniaturization of very large scale integration circuits, higher frequencies and reduction of supply voltages make embedded systems more susceptible to soft errors (or transient errors). Soft errors affect the processor's pipeline and hence its data and control flows. Specifically, errors in control flows can change program's execution sequence, which might be catastrophic for safety-critical applications. Several state-of-the-art techniques are available for control flow error checking (CFEC). Software-based techniques suffer from increased code size overhead and can have a negative impact on energy consumption. On the other hand, hardware-based schemes incur high hardware and area costs. In this paper, a low-cost CFEC scheme is proposed that exploits available redundancies in the processor's pipeline; a branch target buffer stores the target addresses of taken branches, a short backward branch detector stores short loop branch targets and an arithmetic logic unit generates branch target addresses using the low-order branch displacement bits of branch instructions. The proposed CFEC scheme uses these redundancies to detect and recover from control flow errors in the pipeline with low energy overhead of 0.9% and performance overhead of 0.8%, while its error coverage ranges from 86% to 99%.