Fault buffers Enabling near-true voltage scaling in variation-sensitive L1 caches

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Voltage scaling can be applied to cache memories to reduce their energy consumptions. However, reduced supply voltage to the cache memories increases the number of defective SRAM cells due to process variations, which will decrease their yields and nullify the benefits of voltage scaling. To mitigate this problem, we propose a fault buffer-based scheme for L1 caches. Faults are identified and isolated at the granularity of individual words in the L1 caches. Actively used faulty cache words are dynamically allocated in the fault buffers. The fault buffers are organized as multiple banks for low cost implementation and can be dynamically reconfigured to reflect varying performance demands of programs. This dynamic scheme is shown to be more energy- and area-efficient than, and to be performing comparably to, the previously proposed static schemes.
Publisher
SPRINGER
Issue Date
2013-06
Language
English
Article Type
Article
Keywords

DESIGN; YIELD; MODEL; CMOS

Citation

DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, v.17, no.2, pp.411 - 438

ISSN
0929-5585
DOI
10.1007/s10617-012-9104-z
URI
http://hdl.handle.net/10203/190109
Appears in Collection
CS-Journal Papers(저널논문)
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