Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

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A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal-oxide-semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes.
Publisher
Institute of Physics Publishing
Issue Date
2013-12
Language
English
Article Type
Article
Citation

JOURNAL OF SEMICONDUCTORS, v.34, no.12, pp. -

ISSN
1674-4926
DOI
10.1088/1674-4926/34/12/125001
URI
http://hdl.handle.net/10203/189480
Appears in Collection
EE-Journal Papers(저널논문)
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