A structured ASIC, one kind of programmable logic device (PLD), consists of a homogeneous array of programmable logic elements, or called tiles. The architecture of each tile is supposed to be very general so that any kind of logic can be implemented on it; this is the main reason why a structured ASIC has an inherently limited performance, together with a large area requirement compared to an ASIC. This balances the little mask cost of structured ASIC. We tilt this balance by introducing a small number of different types of tile, each with its own architecture, which can be deployed across different designs by the use of a simple blocking mask. This is made possible by a new photolithography concept called selectively patterned masks (SPM), which we propose. We address the practical issues of SPM, including mask cost and manufacturing time. We introduce the heterogeneous array of programmable logic (HAPL), which is a new structured ASIC which takes advantage of SPM. HAPL has its own tile and routing architectures, and supporting CAD tools for packing and routing. Extensive experiments in 45-nm technology are used to assess HAPL and compare it with ASIC. A HAPL design that is optimized for area is about twice the size of its ASIC counterpart. A delay-optimized HAPL design exhibits a post-layout delay which is, on average, 1.35 that of an equivalent ASIC.