Modeling and analysis of 3D-power distribution network (3D-PDN) in TSV-based 3D-IC based on a segmentation method = 구조 분할 방법에 기반한 관통 실리콘 비아 기반 3차원 IC 내 3차원 전력 분배망의 모델링 및 분석

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To estimate the simultaneous switching noise (SSN) generation and evaluate the PDN designs in TSV-based 3D-ICs, the impedance properties of the 3D-PDNs in the 3D-ICs are required. In this research, a new modeling method for the estimation of impedance properties of the 3D-PDN in a TSV-based 3D-IC is proposed. The main approach of the modeling method is to decompose the 3D-PDN into the on-chip PDNs in which the on-chip decoupling capacitors are embedded and the P/G TSVs and calculate the impedance properties of the decomposed PDN structures independently. After the decomposition and the calculation, the impedance proper-ties of the 3D-PDN are estimated by using a segmentation method. In order to calculate the impedance properties of the decomposed PDN structures of the 3D-PDN, three kinds of modeling methods are introduced. First, an equation-based modeling method to estimate the impedance properties of the on-chip PDN is proposed. Second, a modeling method to estimate the impedance properties of the on-chip PDN including the on-chip decoupling capacitors is proposed. Third, a new modeling method to estimate the impedance properties of 3D-PDN is proposed. In order to verify the modeling methods of the on-chip PDN and the on-chip PDN including the on-chip decoupling capacitors, the on-chip PDN and the on-chip PDN comprising the on-chip decoupling capacitors have been fabricated. These modeling methods have been verified by comparing with the experiment results in the frequency domain from 0.1GHz to 20GHz. The proposed modeling method of the 3D-PDN has been verified by comparing with the simulation results from CST MWS in the frequency range of 0.1 GHz to 20 GHz. The impedance property of the 3D-PDN is analyzed. In addition, using the proposed models, we analyze the impedance properties of the 3D-PDN with respect to the parameter variations of the 3D-PDN design.
Advisors
Kim, Joung-Horesearcher김정호researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2011
Identifier
467901/325007  / 020093045
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 2011.2, [ vi, 48 p. ]

Keywords

3D-power distribution network; on-chip PDN; on-chip decoupling capacitor; power/ground TSV; 3차원 전력 분배망; 칩 단위 전력 분배망; 칩 단위 감결합 커패시터; 전압/접지 관통 실리콘 비아; 구조 분할 방법; segmentation method

URI
http://hdl.handle.net/10203/180716
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=467901&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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