To estimate the simultaneous switching noise (SSN) generation and evaluate the PDN designs in TSV-based 3D-ICs, the impedance properties of the 3D-PDNs in the 3D-ICs are required. In this research, a new modeling method for the estimation of impedance properties of the 3D-PDN in a TSV-based 3D-IC is proposed. The main approach of the modeling method is to decompose the 3D-PDN into the on-chip PDNs in which the on-chip decoupling capacitors are embedded and the P/G TSVs and calculate the impedance properties of the decomposed PDN structures independently. After the decomposition and the calculation, the impedance proper-ties of the 3D-PDN are estimated by using a segmentation method. In order to calculate the impedance properties of the decomposed PDN structures of the 3D-PDN, three kinds of modeling methods are introduced. First, an equation-based modeling method to estimate the impedance properties of the on-chip PDN is proposed. Second, a modeling method to estimate the impedance properties of the on-chip PDN including the on-chip decoupling capacitors is proposed. Third, a new modeling method to estimate the impedance properties of 3D-PDN is proposed. In order to verify the modeling methods of the on-chip PDN and the on-chip PDN including the on-chip decoupling capacitors, the on-chip PDN and the on-chip PDN comprising the on-chip decoupling capacitors have been fabricated. These modeling methods have been verified by comparing with the experiment results in the frequency domain from 0.1GHz to 20GHz. The proposed modeling method of the 3D-PDN has been verified by comparing with the simulation results from CST MWS in the frequency range of 0.1 GHz to 20 GHz. The impedance property of the 3D-PDN is analyzed. In addition, using the proposed models, we analyze the impedance properties of the 3D-PDN with respect to the parameter variations of the 3D-PDN design.