Speed enhancement 기법을 포함하는 45nm 7b 1.1V 800MS/s, 1.25V 1GS/s nonbinary 2bit/cycle SAR ADC 의 설계 = A 45nm CMOS, 7-b, 1.1-V 800-MS/s, 1.25-V 1-GS/s, Nonbinary 2-b/cycle SAR ADC with Speed Enhancement Techniques

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dc.contributor.advisor류승탁-
dc.contributor.advisorRyu, Seung-Tak-
dc.contributor.author홍혁기-
dc.contributor.authorHong, Hyeok-Ki-
dc.date.accessioned2013-09-12T01:55:16Z-
dc.date.available2013-09-12T01:55:16Z-
dc.date.issued2012-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=486853&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/180702-
dc.description학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2012.2, [ v, 34p ]-
dc.languagekor -
dc.publisher한국과학기술원-
dc.subject아날로그디지털컨버터-
dc.subjectADC-
dc.subject2b/cycle-
dc.subjectNonbinary-
dc.subjectDynamic latch-
dc.subjectSAR ADC-
dc.titleSpeed enhancement 기법을 포함하는 45nm 7b 1.1V 800MS/s, 1.25V 1GS/s nonbinary 2bit/cycle SAR ADC 의 설계 = A 45nm CMOS, 7-b, 1.1-V 800-MS/s, 1.25-V 1-GS/s, Nonbinary 2-b/cycle SAR ADC with Speed Enhancement Techniques-
dc.typeThesis(Master)-
dc.identifier.CNRN486853/325007 -
dc.description.department한국과학기술원 : 전기및전자공학과, -
dc.identifier.uid020103695-
dc.contributor.localauthor류승탁-
dc.contributor.localauthorRyu, Seung-Tak-
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