Speed enhancement 기법을 포함하는 45nm 7b 1.1V 800MS/s, 1.25V 1GS/s nonbinary 2bit/cycle SAR ADC 의 설계 = A 45nm CMOS, 7-b, 1.1-V 800-MS/s, 1.25-V 1-GS/s, Nonbinary 2-b/cycle SAR ADC with Speed Enhancement Techniques

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Advisors
류승탁researcherRyu, Seung-Tak
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2012
Identifier
486853/325007  / 020103695
Language
kor
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2012.2, [ v, 34p ]

Keywords

아날로그디지털컨버터; ADC; 2b/cycle; Nonbinary; Dynamic latch; SAR ADC

URI
http://hdl.handle.net/10203/180702
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=486853&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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