Integrated design flow for pulsed latch ASIC circuits

Abstract

Pulsed latch, a latch driven by a brief clock pulse, has advantage of flip-flop and latch. Pulsed latch based circuit has the convenience of timing verification similiar to flip-flop based circuits, while retaining superior design parameters of latches over flip-flop, such as sequencing overhead, area and power consumption. In ASIC design, pulsed latches are supported by CAD tools only in clock tree synthesis. Current design flow for pulsed latches cannot guarantee load limit of pulse generator and prevent distortion of pulse.

In this thesis, we propose a new design flow which supports pulsed latch from logic synthesis. New design flow can be applied easily to current ASIC design since it is based on current ASIC design flow. We remodel timing model so that pulsed latch is regarded as faster flip-flop during logic synthesis. A new pulse generator which is less sensitive to clock transition is also introduced. We also set load limit of pulse generator to prevent distortion of pulse using clock-to-Q delay (Tcq) of connected latches. For the placement, we propose a new method to set bounding box so that pulsed latches and pulse generator are placed closely. It satisfies all the load limits of pulse generator within 4\% wire length overhead. In addition, to solve hold time violations on scan chain in pulsed latch design, we introduce a new scan latch with delayed output for scan chain. A simple algorithm to use both new scan latch and standard latch together is proposed to reduce hold time violations in scan chain. It can reduce buffer area overhead and total area is reduced by 10%.

Pulsed latch based circuit throuth this design flow achieve 10% improvement in area and 19% improvement in power compared to ASIC circuit based on flip-flop.