Low-noise digital phase locked loop using reference multiplication with adaptive calibration = 적응 교정적 기준 주파수 증가를 이용한 저잡음 디지털 위상고정루프

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Designing a low noise fractional-N digital phase locked loop (DPLL) is quite an issue these days. This paper also presents techniques for good noise performance of fractional-N DPLL. The technique includes increasing reference frequency for low phase noise. Increasing reference frequency reduces divide value. Also higher reference frequency increases operation frequency of delta-sigma modulator (DSM) which is one of the major noise source in fractional-N DPLL. These may lead to better noise performance of DPLL. If DPLL contains oversampling time to digital converter (TDC), increased reference frequency will alleviate its requirements. In order to increase reference frequency, integer-N type frequency synthesizer based on open loop scheme is implemented. This scheme can lower the phase noise caused by increasing reference frequency. However, it has static mismatch which can bring severe degradation of noise performance. Especially, it causes the reference spur. To solve this problem, benefit from digital scheme can be derived. By adopting adaptive filter, static noise caused by mismatch can be reduced. The proposed DPLL fabricated in 65nm CMOS process.
Advisors
Cho, Seong-Hwanresearcher조성환
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2012
Identifier
509453/325007  / 020104340
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2012.8, [ iv, 37 p. ]

Keywords

DPLL; 위상고정루프; PLL

URI
http://hdl.handle.net/10203/180631
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=509453&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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