A Study of the CMOS RF front-end circuits for 60 GHz wireless communications

Abstract

In this paper, RF Front-End circuits for the 60 GHz wireless communication are studied. The performances of the RF Front-End circuits at 60 GHz are quiet limited comparing to the performance of the RF circuits under 10 GHz. Main performance is-sues are gain, efficiency, and output power. Also wide operating bandwidth of the 60 GHz system with low noise figure is hard to achieve in designing phase shifter IP. Firstly the study focuses on transistor architecture and bias of the transistor. To en-hance gain bandwidth product, this thesis drives fmax equation with design parameters and the result of the fmax versus transistor geometry is plotted. In this process, optimum transistor architecture for enhancing gain bandwidth product can be determined. The 60 GHz transistor bias points under the concept of the current density for LNA and PA are defined to standardize bias condition of the millimeter transistors. The miller compensated transformer coupled PA is suggested to solve the gain and efficiency problems. The effect of the miller compensation capacitor Cm is explained in boosting gain and reducing phase distortion. The measurement results verify the oper-ating algorithm of the inserting Cm. The cascade power combining PA is also suggested. The algorithm of the power combination is equated and simulated in this thesis. Due to adopting the new power combination method, the performance of gain, efficiency, and output power of the newly proposed PA are enhanced largely. The wideband digitally controlled 5 bit phase shifter is studied, designed, and meas-ured in the last chapter. The main contribution of the phase shifter is proposing series resonant matching of the 2 stage poly-phase filter. Its operation is analyzed and con-firmed for using in phase shifter. Measure results shows 2.5 dB noise reduction and 9 dB gain enhancement.