Energy-efficient embedded media application processor에너지 효율적인 임베디드 미디어 어플리케이션 프로세서

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Application Processor (AP) is the main chip on today’s handheld devices such as smartphones, tablet PCs, or portable media players. Unlike PC-based system, there are three main limitations on embedded environment; battery (power), resource (area), and bandwidth limitations. Based on the heterogeneous many-core platform which includes various functional IPs on a single silicon die, power dissipation, implementation area, and memory bandwidth should be carefully considered in AP design. Among the heterogeneous functional IPs on AP, we focused on programmable accelerators for multimedia applications such as GPU, ISP, and DSP which are responsible for intensive multimedia workloads in APs. Multimedia applications can be classified into two types; 2-dimensional (2D) image analysis applications such as image processing or computer vision and 3D image synthesis applications such as 3D graphics. Based on the system which can accommodate those 2D/3D image analysis/synthesis applications, more complex multimedia contents such as augmented reality (AR), 3D display, and 3D reconstruction can be processed on the same hardware platform. Media contents processing includes both data-intensive memory operations and compute-intensive non-memory operations. In order to support various media applications on a single mobile platform, both operations should be supported in an energy-efficient way. In this dissertation, a heterogeneous multimedia processor (media application processor; MAP) is presented for media contents processing on mobile devices. It includes reconfigurable hardware components such as a data transceiver with reconfigurable output drivers, a multi-purpose micro-operation cache, and mode-configurable parallel processing cores for general-purpose media contents processing on battery-limited embedded environment. The data transceiver and the multi-purpose micro-operation cache support data-intensive memory operations, while the mode-configurable parallel processin...
Advisors
Kim, Lee-Supresearcher김이섭
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
2013
Identifier
513096/325007  / 020107033
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 2013.2, [ viii, 133 p. ]

Keywords

그래픽 연산 유닛; 어플리케이션 프로세서; parallel processing; many-core; si-interposer; 3D-IC; memory bandwidth; cache architecture; augmented reality; graphics processing unit; application processor; 증강 현실; 캐시 구조; 메모리 대역폭; 3차원 집적회로; 실리콘 인터포저; 멀티코어; 병렬처리; 전력관리; power management

URI
http://hdl.handle.net/10203/180119
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=513096&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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