Stacked-FET linear SOI CMOS SPDT antenna switch with input P1 dB greater than 40 dBm

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The power handling capability is the most stringent specification for antenna switches, and this is dominated by a significant amount of leakage current of off-state FETs. For achieving maximum power handling capability of antenna switches, new DC I-V (FFI-V) characterization method to characterize RF P-1dB point of off-state FETs is proposed and experimental study on optimum DC gate and body bias is performed based on proposed FFI-V method. Using R-on and C-off of minimum channel length MOSFETs at aforementioned optimum DC bias point, antenna switch design methodology for maximum power handling capability and minimum insertion loss is established. The designed SOI CMOS SPDT antenna switch integrated with switch controller shows insertion loss less than 0.5 dB and input P-1dB greater than + 40 dBm.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2012-12
Language
English
Article Type
Article
Keywords

T/R SWITCH

Citation

IEICE ELECTRONICS EXPRESS, v.9, no.24, pp.1813 - 1822

ISSN
1349-2543
DOI
10.1587/elex.9.1813
URI
http://hdl.handle.net/10203/174956
Appears in Collection
EE-Journal Papers(저널논문)
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