3D 적층칩을 위한 Edge traces 공정에 관한 연구

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dc.contributor.author이승섭-
dc.contributor.author김선락-
dc.contributor.author이재학-
dc.contributor.author유중돈-
dc.contributor.author송준엽-
dc.date.accessioned2013-03-29T19:10:19Z-
dc.date.available2013-03-29T19:10:19Z-
dc.date.created2012-10-30-
dc.date.issued2011-10-
dc.identifier.citation2011 한국정밀공학회 추계학술대회, v., no., pp. --
dc.identifier.urihttp://hdl.handle.net/10203/173091-
dc.languageKOR-
dc.publisher한국정밀공학회-
dc.title3D 적층칩을 위한 Edge traces 공정에 관한 연구-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.publicationname2011 한국정밀공학회 추계학술대회-
dc.identifier.conferencecountrySouth Korea-
dc.contributor.localauthor이승섭-
dc.contributor.nonIdAuthor김선락-
dc.contributor.nonIdAuthor이재학-
dc.contributor.nonIdAuthor유중돈-
dc.contributor.nonIdAuthor송준엽-
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ME-Conference Papers(학술회의논문)
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