On-chip network design considerations for compute accelerators

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Publisher
Institute of Electrical and Electronics Engineers
Issue Date
2010-09-11
Language
ENG
Citation

19th International Conference on Parallel Architectures and Compilation Techniques, PACT 2010, v.0, no.0, pp.535 - 536

ISSN
1089-795X
URI
http://hdl.handle.net/10203/167067
Appears in Collection
EE-Conference Papers(학술회의논문)
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