DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Y.G. | ko |
dc.contributor.author | Hong, H.S. | ko |
dc.contributor.author | Bae, Doo-Hwan | ko |
dc.contributor.author | Cha, Sungdeok | ko |
dc.date.accessioned | 2009-12-29T04:47:13Z | - |
dc.date.available | 2009-12-29T04:47:13Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1999-08 | - |
dc.identifier.citation | IEE PROCEEDINGS: SOFTWARE, v.146, no.4, pp.187 - 192 | - |
dc.identifier.issn | 1462-5970 | - |
dc.identifier.uri | http://hdl.handle.net/10203/15990 | - |
dc.description.abstract | The paper discusses the application of state diagrams in UML to class testing. A set of coverage criteria is proposed based on control and data flow in UML state diagrams and it is shown how to generate test cases satisfying these criteria from UML state diagrams. First, control flow is identified by transforming UML state diagrams into extended finite state machines (EFSMs). The hierarchical and concurrent structure of states is flattened and broadcast communications are eliminated in the resulting EFSMs. Second, data flow is identified by transforming EFSMs into flow graphs to which conventional data flow analysis techniques can be applied. © IRE, 1999. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | Institute of Electrical Engineers | - |
dc.title | Test cases generation from UML state diagrams | - |
dc.type | Article | - |
dc.identifier.scopusid | 2-s2.0-0033170385 | - |
dc.type.rims | ART | - |
dc.citation.volume | 146 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 187 | - |
dc.citation.endingpage | 192 | - |
dc.citation.publicationname | IEE PROCEEDINGS: SOFTWARE | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Bae, Doo-Hwan | - |
dc.contributor.nonIdAuthor | Kim, Y.G. | - |
dc.contributor.nonIdAuthor | Hong, H.S. | - |
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