DSpace at KOASAS: Parallelized VLSI architecture of single stack based list sphere decoder

DSpace at KOASAS

College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

Parallelized VLSI architecture of single stack based list sphere decoder

Cited 0 time in webofscience

Cited 0 time in

Hit : 276
Download : 0

Export

Kim H.-S. / Seo S.-H. / Park, Sin Chong researcher

Issue Date: 2006-11-16

Language: ENG

Citation: 8th International Conference on Signal Processing, ICSP 2006, v.1

URI: http://hdl.handle.net/10203/143084

Appears in Collection: EE-Conference Papers(학술회의논문)

Files in This Item: There are no files associated with this item.

Display Full Item Record

qr_code

트윗하기

KOASAS

Knowledge Service Development Team, KAIST 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea. T. 82-42-350-4493 Email. koasas@kaist.ac.kr
Copyright © 2016. Korea Advanced Institute of Science and Technology. All Rights Reserved.

KOASAS

KOASAS

Browse

Parallelized VLSI architecture of single stack based list sphere decoder

KOASAS

Communities & Collections