Leakage power minimization for the synthesis of parallel multiplier circuits

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Issue Date
2004-04-26
Language
ENG
Citation

Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era, pp.166 - 169

URI
http://hdl.handle.net/10203/139802
Appears in Collection
RIMS Conference Papers
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