A Floorplan-based Planning Methodology for Power and Clock Distribution in ASICs

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 1234
  • Download : 0
Issue Date
1999-06
Language
ENG
Citation

36th Design Automation Conference(DAC), pp.766 - 771

URI
http://hdl.handle.net/10203/133080
Appears in Collection
EE-Conference Papers(학술회의논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0