MDSP-II: A 16-bit DSP with mobile communication accelerator

Abstract

This paper describes a 16-bit programmable fixed-point digital signal processor, called MDSP-II, for mobile communication applications. The instruction set of MDSP-II was determined after a careful analysis of the global system for mobile communications (GSM) baseband functions. An application-specific hardware block called the mobile communication accelerator (MCA) was incorporated on-chip to accelerate the execution of the hey operations frequently appearing in Viterbi equalization. With the assistance of MCA, the GSM baseband functions, which need 53 million instructions per second (MIPS) on the general-purpose digital signal processors, can be performed only with 19 MIPS. The MDSP-II was implemented with a 0.6-mu m triple-layer metal CMOS process on a 9.7 x 9.8 mm(2) silicon area and was operated up to 50 MHz clock frequency.