An energy-efficient mobile vertex processor with multithread expanded VLIW architecture and vertex caches

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In this paper, a 3-D vertex processor with a floating-point four-threaded and four-issue expanded VLIW architecture and vertex caches for mobile multimedia applications is proposed. The multi-threaded datapath prevents data hazards, and the multi-issue expanded VLIW architecture enables the processor to have an opportunity to execute instructions in parallel and a well-balanced way. The efficient vertex caches are proposed and implemented for the embedded vertex processors to accelerate its geometry operations and to save bandwidth between hosts and vertex processors. The proposed architecture with the vertex caches reduces the average total energy dissipation of 44.7% compared to a conventional single-threaded SIMD architecture, and the proposed vertex processor achieves 120 Mvertices/s of geometry performance which is 3.3 times faster than the previous result, and it supports OpenGL ES 2.0 and Vertex Shader Model 3.0. The processor is implemented in a 0.18-mu m 1P4M CMOS process, and the operating frequency is 100 MHz.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2007-10
Language
English
Article Type
Article; Proceedings Paper
Keywords

PIPELINE

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.42, pp.2257 - 2269

ISSN
0018-9200
URI
http://hdl.handle.net/10203/12270
Appears in Collection
EE-Journal Papers(저널논문)
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