A 20 Gb/s 1 : 4 DEMUX without inductors and low-power divide-by-2 circuit in 0.13 mu m CMOS technology

Abstract

In this paper, a 20 Gb/s 1:4 DEMUX without inductors is presented. A coupled latch with shared current source and buffer insertion scheme improves the signal bandwidth. A divide-by-2 circuit with a static frequency divider and a delay-locked loop achieves low power consumption and enhanced timing margin without the degradation of the divider sensitivity. A horizontal eye opening is 71.3%, and a vertical eye opening is 52%. The test chip fabricated in a 0.13 mu m process consumes 210 mW from 1.2 V logic supply.