25.6Gbit/s horizontally and vertically accessible embedded multiport SRAM

An architecture for an embedded 8-port SRAM with 256 bit simultaneous horizontal and vertical data access for adjacent or alternate addresses is proposed. This architecture makes possible four kinds of address configurations which are effective in video applications by selecting multiple word lines and one of four bit lines for each column multiplexer. The proposed SRAM provides 25.6 Gbit/s of high bandwidth.
Publisher
IEE-INST ELEC ENG
Issue Date
1999-10
Language
ENG
Description

Electronics Letters

Keywords

VIDEO

Citation

ELECTRONICS LETTERS, v.35, no.21, pp.1823 - 1825

ISSN
0013-5194
DOI
10.1049/el:19991248
URI
http://hdl.handle.net/10203/11108
Appears in Collection
EE-Journal Papers(저널논문)
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