Performance modeling of resonant tunneling-based random-access memories

Resonant tunneling-based random-access memories (TRAMs) have recently garnered a great amount of interest among memory designers due to their intrinsic merits such as reduced power consumption by elimination of refreshing operation, faster read and write cycles, and improved reliability in comparison to conventional silicon dynamic random access memories (DRAMs). In order to understand the precise principle of operation of TRAM memories, an in-depth circuit analysis has been attempted in this paper and analytical models for memory cycle time, soft error rate, and power consumption have been derived. The analytical results are then validated by simulation experiments performed with HSPICE. These results are then compared with conventional DRAMs to establish the claim of superiority of TRAM performance to DRAM performance.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2005-07
Language
ENG
Keywords

DEVICES

Citation

IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.4, no.4, pp.472 - 480

ISSN
1536-125X
DOI
10.1109/TNANO.2005.851288
URI
http://hdl.handle.net/10203/1091
Appears in Collection
EE-Journal Papers(저널논문)
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