A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS

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In this paper, a crosstalk compensation scheme for high speed single-ended on-chip signaling is presented. To reduce the effect of crosstalk in bandwidth enhanced channel employing capacitively driven interconnect, a crosstalk feed-forward equalizer is proposed, which compensates for the low-pass nature of the crosstalk. The proposed scheme is verified using a three-channel 10 mm on-chip interconnect implemented in 130 nm CMOS process. Measurement results show that the proposed transceiver effectively removes the crosstalk for data rates of up to 2.5-Gb/s while consuming 0.96 mW, which corresponds to energy efficiency of 0.41 pJ/bit.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2012-01
Language
English
Article Type
Article
Keywords

COMMUNICATION

Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.59, no.1, pp.124 - 136

ISSN
1549-8328
DOI
10.1109/TCSI.2011.2161394
URI
http://hdl.handle.net/10203/104050
Appears in Collection
EE-Journal Papers(저널논문)
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