Homogeneous Stream Processors With Embedded Special Function Units for High-Utilization Programmable Shaders

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We embed special function units (SFUs) in homogeneous stream processors (SPs) within a graphics processing unit (GPU), to improve its performance in running modern programmable shaders, which make poor use of a single-instruction multiple-data (SIMD) architecture. We also compact instructions, so as to reduce the size of the instruction memory, and reduce area requirements by using a partial SFU in SPs, and a lookup table which is shared between multiple SFUs. The result is an increase of 88% in utilization and a reduction in the normalized area-delay product of 27%, compared to a baseline SIMD architecture. We verified our architecture on an field-programmable gate-array evaluation platform with an ARM9 host processor and a full 3-D graphics pipeline.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2012-09
Language
English
Article Type
Article
Keywords

ARCHITECTURE; GRAPHICS

Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.9, pp.1691 - 1704

ISSN
1063-8210
DOI
10.1109/TVLSI.2011.2161499
URI
http://hdl.handle.net/10203/103566
Appears in Collection
EE-Journal Papers(저널논문)
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