High performance memory mode control for HDTV decoders

To increase the bandwidth of synchronous memories that are widely adopted for HDTV decoder systems, a predictive mode control scheme is proposed in this paper. Memory latency and energy consumption can be reduced by effectively managing the states of banks. The local access history of each bank is considered to predict the memory mode. In a HDTV decoder system, experimental results show that the proposed scheme reduces the memory latency and the energy consumption by 18.8% and 23.3%, respectively, over the conventional scheme that always keeps the memory in idle state. A hardware architecture and its VLSI implementation are also presented(1).
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2003-11
Language
ENG
Keywords

SYNCHRONOUS DRAM; ARCHITECTURE; DESIGN

Citation

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, v.49, pp.1348 - 1353

ISSN
0098-3063
URI
http://hdl.handle.net/10203/1004
Appears in Collection
EE-Journal Papers(저널논문)
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