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Showing results 129401 to 129420 of 275509
| Minimizing Clonal Variation during Mammalian Cell Line Engineering for Improved Systems Biology Data Generation Grav, Lise Marie; Sergeeva, Dania; Lee, Jae Seong; de Mas, Igor Marin; Lewis, Nathan E.; Andersen, Mikael Rordam; Nielsen, Lars Keld; et al, ACS SYNTHETIC BIOLOGY, v.7, no.9, pp.2148 - 2159, 2018-09 |
| Minimizing Collision among Social Groups in Wide-Open Spaces Rojas, Francisco Arturo; Yang, Hyun-Seung, CyerWorlds International Conference(CyberWorlds 2014), CyberWorlds, 2014-10-06 |
| Minimizing Communications in Decentralized Greedy Task Allocation Kim, Keumseong; Kim, Hoyeon; Choi, Han-Lim, JOURNAL OF AEROSPACE INFORMATION SYSTEMS, v.16, no.8, pp.340 - 345, 2019-08 |
Minimizing cross sectional pulse width difference between central and edge parts of SBS compressed beam Wang, Hongli; Cha, Seongwoo; Kong, Hong Jin; Wang, Yulei; Lu, Zhiwei, OPTICS EXPRESS, v.27, no.2, pp.1646 - 1659, 2019-01 |
| Minimizing Data Center Uninterruptable Power Supply Overload by Server Power Capping Al Hazemi, Fawaz; Lorincz, Josip; Mohammed, Alaelddin Fuad Yousif, IEEE COMMUNICATIONS LETTERS, v.23, no.8, pp.1342 - 1346, 2019-08 |
| Minimizing Driving Risk of Mobile Robots by Combining a Goal Guidance Vector Algorithm with Reactive Navigation 최근하; 김수현, 한국정밀공학회지, v.38, no.2, pp.103 - 113, 2021-02 |
| Minimizing due date related measures for a single machine scheduling problem with outsourcing allowed Lee, Ik Sun; Sung, Chang Sup, EUROPEAN JOURNAL OF OPERATIONAL RESEARCH, v.186, no.3, pp.931 - 952, 2008-05 |
| Minimizing Due Date Related Peformance Measures on Two Batch Processing Machines Sung, Chang Sup, EUROPEAN JOURNAL OF OPERATIONAL RESEARCH, v.147, no.3, pp.644 - 656, 2003-06 |
| Minimizing Early and Tardy Penalties in a Job Sequencing Problem Using Genetic Algorithms Lee, Chae Young, Korean/Japan Joint Conference on Expert Systems, pp.609 - 632, 1993 |
| Minimizing Effect of Input Filter Capacitor in a Digital Boundary Conduction Mode Power Factor Corrector Based on Time-Domain Analysis Kim, Jong-Woo; Moon, Gun-Woo, IEEE TRANSACTIONS ON POWER ELECTRONICS, v.31, no.5, pp.3827 - 3836, 2016-05 |
| Minimizing Energy Consumption Through Traffic Offloading in HetNets With Two-Class Traffic Song, Yujae; Kong, Peng-Yong; Han, Youngnam, IEEE COMMUNICATIONS LETTERS, v.19, no.8, pp.1394 - 1397, 2015-08 |
| Minimizing Energy Use for Surface Reactions by Using Both Light and Heat; Light-Assisted Surface Reactions on Metal Catalysts Kim, Chanyeon; Lee, Hyunjoo, 2018 MRS Fall Meeting, Materials Research Society, 2018-11-28 |
| Minimizing expected losses in perturbation models with multidimensional parametric min-cuts Kim, Adrian; Jung, Kyomin; Lim, Yongsub; Tarlow, Daniel; Kohli, Pushmeet, 31st Conference on Uncertainty in Artificial Intelligence, UAI 2015, pp.435 - 443, Association for Uncertainty in Artificial Intelligence, 2015-07 |
| Minimizing Human Intervention for Constructing Korean Part-of-Speech Tagged Corpus Lee D.-G.; Hong G.; Lee S.K.; Rim H.-C., IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E93D, no.8, pp.2336 - 2338, 2010 |
| Minimizing Leakage Magnetic Field of Wireless Power Transfer Systems Using Phase Difference Control Woo, Seongho; Shin, Yujun; Lee, Changmin; Rhee, Jaewon; Ahn, Jangyong; Moon, Jungick; Son, Seokhyeon; et al, ENERGIES, v.15, no.21, 2022-11 |
| Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping Heo, S; Shin, Youngsoo, ISOCC, IEEE, 2007-10-16 |
| Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping Sewan Heo; Youngsoo Shin, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE , v.15, no.7, pp.215 - 220, 2007-12 |
| Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping = 플립플랍 비대칭화와 테크놀로지 매핑을 통한 순차회로의 누설전류 감소link Heo, Se-Wan; 허세완; et al, 한국과학기술원, 2007 |
| Minimizing leakage power in sequential circuits by using mixed $V_t$ Flip-Flops = 혼합 문턱전압 플립플랍을 이용한 순차 회로의 누설 전류 감소 기법link Kim, Jae-Hyun; 김재현; et al, 한국과학기술원, 2008 |
| Minimizing leakage power in sequential circuits by using mixed Vt flip-flops Kim, J.; Shin, Youngsoo, 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD, pp.797 - 802, 2007-11-04 |
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