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Showing results 1 to 4 of 4

1
Calibration of Compact Resist Model Through CNN Training

Kwon, Yonghwi; Shin, Youngsoo, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.36, no.2, pp.180 - 187, 2023-05

2
Memory-Augmented Convolutional Neural Networks With Triplet Loss for Imbalanced Wafer Defect Pattern Classification

Hyun, Yunseung; Kim, Heeyoung, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.33, no.4, pp.622 - 634, 2020-11

3
Semi-Supervised Multi-Label Learning for Classification of Wafer Bin Maps With Mixed-Type Defect Patterns

Lee, Hyuck; Kim, Heeyoung, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.33, no.4, pp.653 - 662, 2020-11

4
The Impact of Processing Time Variations on Swap Sequence Performance in Dual-Armed Cluster Tools

Lee, Jun-Ho; Kim, Hyun-Jung, IEEE TRANSACTIONS ON AUTOMATION SCIENCE AND ENGINEERING, v.20, no.4, pp.2668 - 2677, 2023-10

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