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Showing results 32501 to 32520 of 275826
| Area and power minimization in controller synthesis = 제어기 합성에서의 면적과 파워의 최소화link Hong, Se-Kyoung; 홍세경; et al, 한국과학기술원, 1995 |
| Area comparison in Alexandrov surfaces = 알렉산드로프 곡면에서의 넓이 비교정리link Oh, Seung-Taik; 오승택; et al, 한국과학기술원, 1996 |
| Area Efficient Algorithms for Upward Straight-Line Tree Drawings Chwa, Kyung Yong, , 1996-01-01 |
| Area efficient neuromorphic circuit based on stochastic computation 윤기원; 최수형; 신영수, 한국반도체학술대회, 대한전자공학회, 2017-02-15 |
| Area efficient neuromorphic circuit based on stochastic computation Yoon, Kiwon; Choi, Suhyeong; Shin, Youngsoo, 13th International SoC Design Conference, ISOCC 2016, pp.73 - 74, Institute of Electrical and Electronics Engineers Inc., 2016-10-23 |
| Area efficient pipelined VLSI implementation of list sphere decoder Lee J.; Park, Sin Chong, 2006 Asia-Pacific Conference on Communications, APCC, 2006-08-31 |
| Area gestures for a laptop computer enabled by a hover-tracking touchpad Choi, Sangwon; Gu, Jiseong; Han, Jaehyun; Lee, Geehyuk, The 10th Asia Pacific Conference on Computer Human Interaction, pp.119 - 124, Human Centered Design Organization and ACM, 2012-08-30 |
| Area light source-triggered latent angiogenic molecular mechanisms intensify therapeutic efficacy of adult stem cells Kim, Yu-Jin; Kim, Sung-Won; Im, Gwang-Bum; Kim, Yeong Hwan; Jeong, Gun-Jae; Jeon, Hye Ran; Kim, Dong-Ik; et al, BIOENGINEERING & TRANSLATIONAL MEDICINE, v.7, no.1, 2022-01 |
| Area optimization algorithms for FSM synthesis and FPGA technology mapping = FSM 합성과 FPGA 기술 매핑을 위한 면적 최적화 알고리즘link Park, Sung-Soo; 박성수; et al, 한국과학기술원, 1995 |
| Area Residence Time Modeling in PCS Networks Lee, Ki-Dong; Kim, Sehun, 한국경영과학회/대한산업공학회 '99 춘계공동학술대회, The Korean Operations Research and Management Science Society, 1999 |
| Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory Jin, Y; Shihab, M; Jung, Myoungsoo, MemoryForum, IEEE, 2014-06-14 |
| Area-based Velocimetry Using TDLAS for Low-speed Flow Jung, Sion; Shim, Hanseul; Kim, Gyeongrok; PARK, GISU, JOURNAL OF MECHANICAL SCIENCE AND TECHNOLOGY, v.37, no.8, pp.1 - 10, 2023-08 |
| Area-contact haptic simulation Kim, S.-Y.; Park, Jinah; Kwon, Dong-Soo, SURGERY SIMULATION AND SOFT TISSUE MODELING, PROCEEDINGS, v.2673, pp.108 - 120, 2003 |
| Area-Contact Haptic Simulation Kim, SY; Park, J; Kwon, Dong-Soo, Proc. Of International Conference on Soft Tissue Modeling and Surgery Simulation, pp.108 - 120, IS4TM'03, 2003-06-12 |
| Area-efficient algorithms for straight-line tree drawings shin cs; kim sk; Chwa, Kyung Yong, COMPUTATIONAL GEOMETRY-THEORY AND APPLICATIONS, v.15, no.4, pp.175 - 202, 2000-04 |
| Area-Efficient and Reusable VLSI Architecture of Decision Feedback Equalizer of QAM Modem Yu, Hyeongseok; Kim, Byung Wook; Cho, Yeon Gon; Cho, Jun Dong; Kim, Jea Woo; Lee, Jae Kon; Park, Hyuncheol; et al, Asia and South Pacific Design Automation Conference (ASP-DAC 2001), IEEE, 2001-01-30 |
| Area-Efficient Approach for Generating Quantized Gaussian Noise Choi, Jaejoon; Jung, Jaehwan; Park, In-Cheol, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.63, no.7, pp.1005 - 1013, 2016-07 |
| Area-Efficient Architecture for Joint Estimation of Fine Timing and Interger Carrier Frequency Offsets 김태환; 박인철, The 14th Korean Conference on Semiconductors (KCS 2007), 2007 |
| Area-efficient check node architecture for 5G LDPC decoders = 5G LDPC 복호기를 위한 면적 효율적인 체크 노드 아키텍처link Yang, Byeongku; Park, In-Cheol; et al, 한국과학기술원, 2022 |
| Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors Han S.-W.; Yoon E., ELECTRONICS LETTERS, v.42, no.6, pp.335 - 337, 2006 |
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